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| MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP M66335FP M66335FP FACSIMILE IMAGE DATA PROCESSOR FACSIMILE IMAGE DATA PROCESSOR DESCRIPTION The M66335 is a facsimile image processing controller to turn into binary signals analog signals which have been output through photoelectric conversion by the image sensor. The image processing functions includes peak value detection, uniformity correction, resolution change, MTF compensation, correction, detection of background/character levels, error diffusion, separation of image zones, and designation of regions. This controller contains not only the analog processing circuit, the A/ D converter of a 7-bit flash type and image processing memory, but also the image sensor and the interface circuit to the CODEC (Coder and Decoder). Therefore, this LSI alone is capable of image processing. * Built-in A/D converter of a 7-bit flash type * Built-in image processing memories * * * FEATURES * High speed scan (max. 2 ms/line, typ. 5 ms/line) * Compatibility with up to the B4 (8 pixels/mm, 16 pixels/mm) image * * sensor Generation of control signals for the image sensor (CCD, CIS) For CCD: SH, CK1, CK2, RS For the contact sensor (CIS): SH, CK1, CK2 Built-in analog processing circuit (equivalent to the M64291) Sample and hold circuit Gain control circuit Black level clamping circuit Reference internal power supply for the A/D converter * Uniformity correction memory, Line memory, Error memory, correction memory External output interface for converted binary data Serial output ( M66330) DMA output External output interface for multivalued data DMA transfer of data compensated for uniformity Various image processing functions Uniformity correction Resolution change from 50% to 200% (by the 1% step) MTF compensation (2-dimensional processing, capable of correction for each character/photo) correction (capable of correction for each character/photo) Detection of background/character levels Change to pseudo-halftone * Error diffusion (64 tone steps through 6-bit processing) * Organized dither (64 tone steps through the 8 x 8 matrix) Image zone separation (2-dimensional processing) 5V single power supply APPLICATION Facsimile, word processor and image scanner PIN CONFIGURATION (TOP VIEW) NC GND VCC 62 61 D7 60 D6 59 D5 58 D4 MPU 57 D3 INTERFACE 56 D2 55 D1 54 D0 GND 53 VCC 52 51 TEST6 50 TEST5 49 TEST4 48 TEST3 47 TEST2 TEST PIN 46 TEST1 45 TEST0 44 TESTI 43 TESTO VCC 42 41 GND 64 63 NC 65 A0 66 A1 67 A2 68 A3 69 MPU INTERFACE A4 70 CS 71 RD 72 WR 73 RESET 74 DAK 75 DMA DRQ 76 INTERFACE INT 77 SYSTEM CLOCK SYSCK 78 GND 79 NC 80 SINGLE-LINE CYCLE CLOCK Outline 80P6N-A CONTROL SIGNAL FOR ANALOG SIGNAL PROCESSING CODEC INTERFACE SENSOR INTERFACE SENSOR INTERFACE 1 NC 2 NC 3 VCC ACCK 4 SVID 5 SCLK 6 STIM 7 SRDY 8 PTIM 9 GND 10 VCC 11 RS 12 CK1 13 CK2 14 SH 15 GND 16 VCC 17 AVCC 18 AIN 19 LEVAJ 20 AGND 21 GCAO 22 NC 23 NC 24 M66335FP NC DGND DVCC 38 VBL ADC BLACK REFERENCE OUTPUT 37 36 VWL ADC WHITE REFERENCE OUTPUT 35 ADIN ADC INPUT 34 AVCC Vri+ ADC WHITE REFERENCE INPUT 33 32 AGND Vri- ADC BLACK REFERENCE INPUT 31 30 BCMO 29 BCMV CONTROL SIGNAL FOR 28 BCMI ANALOG SIGNAL 27 C2 PROCESSING 26 C1 NC 25 40 39 NC: No Connection 1 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR BLOCK DIAGRAM ADIN VWL VBL Vri+ Vri35 36 37 33 31 AVCC 18 34 DVCC 38 VCC 3 11 17 42 52 62 ANALOG CONTROL 78 IMAGE PROCESSING SEQUENCE CONTROL SIGNAL 4 SYSCK ACCK AIN LEVAJ C1 C2 BCMI BCMV GCAO BCMO PTIMB RS CK1 CK2 SH 19 20 26 27 28 29 22 30 7-BIT A/D CONVERTER ANALOG SIGNAL PROCESSING CIRCUIT IMAGE ZONE SEPARATION DETECTION OF BACKGROUND/ CHARACTER LEVELS MTF COMPENSATION SELECTION OF CONVERSIONTO-BINARY PROCESSING 8 IMAGE BUS INTERFACE 5 6 7 75 76 77 UNIFORMITY CORRECTION RESOLUTION CHANGE CORRECTION TABLE SRDYB SVID SCLK STIMB DAKB DRQ INT ERROR DIFFUSION DMA CONTROL 9 12 13 14 15 SENSOR CONTROL CORRECTION DATA MEMORY CONVERSION TABLE MEMORY LINE MEMORY ERROR MEMORY DITHER MATRIX ORGANIZED DITHER 74 RESETB 73 WRB 72 RDB 71 CSB 66 } A0 ~ A4 70 54 } D0 ~ D7 61 MPU BUS INTERFACE 2132 39 1016 41 53 63 79 AGND DGND GND Table 1 Image processing functions Image processing functions Reading range Resolution Reading speed Uniformity correction correction MTF compensation Simple conversion to binary Pseudo-halftone Image zone separation Image reduction * A4, B4 * 8 pixels/mm, 16 pixels/mm (for the horizontal scanning direction) * Typ.: 5 ms/line; max.: 2 ms/line * White correction, black correction * Correction range: 50% * Logarithmic correction * Laplacian filter circuit through 2-dimensional processing * Floating slice system through the detection circuit for background/character levels * Error diffusion: 6-bit processing (for 64 tone steps) * Organized dither: 8 x 8 matrix (for 64 tone steps) * 2-dimensional processing through luminance difference * Range of the reduction rate: 50% to 100% (by the 1% step) * Range of the enlargement rate: 100% to 200% (by the 1% step) * CIS image sensor (clock duty: 75%) * CCD image sensor * The sample/hold circuit, gain control amplifier, black level clamping circuit, and 7-bit A/D converter are built-in. * Capable of outputting the average line of a dropped line and the subsequent line instead of both lines * Capable of outputting the average line of a repeated line and the subsequent line instead of the repeated line * Error buffer memory is built in. * 64W x 6 bits dither memory is built in. * Controlled through the system clock. * Correction memory is built in. * Readable from/writable in MPU * correction memory is built in. * Capable of correction for each character/photo. * Correction memory is built in. * Capable of correction for each character/photo. Specifications Remarks Image enlargement Image sensor control signal Analog processing 2 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR DESCRIPTION OF DIGITAL PIN FUNCTIONS Item Sensor interface Pin name SH Input/output Output Function Outputs the shift pulse signal to transfer electric charges from the sensor's photoconductor component to its transferring component for CCD and the start signal to start the sensor reading circuit for CIS. Outputs the clock pulse signal to sequentially transfer out signaling electric charges from the sensor's transferring component for CCD and the clock pulse signal for the shift register of the sensor reading circuit for CIS. Reversed-phase pulses of CK1 Outputs the reset pulse to return the voltage at the floating capacitor of the CCD sensor to the initial one. Outputs the pulse motor control signal for the reading roller. Transfer start ready signal for data from CODEC Defines the data transfer section to CODEC. Clock signal to transfer image data to CODEC Outputs image data in serial to CODEC DMA request signal to the external DMA controller to output in parallel image data through the MPU bus DMA acknowledge signal from the external DMA controller in response to the above DRQ signal Single-line termination interrupt System clock input pin Single-line cycle clock Input of the system reset. The cycle counter, register, F/F, and latch are reset. Chip select signal for MPU to access the M66335 Control signal for MPU to read data from the M66335 Control signal for MPU to write data to the M66335 Address signal to access various registers inside the M66335 8 bit two way buffer Positive power supply pin GND pin Test input pin. Hold this at "L". Test output pin. Set this open. CK1 Output CK2 RS Output Output PTIM CODEC interface SRDY STIM SCLK SVID DMA interface DRQ Output Input Output Output Output Output DAK INT Clock SYSCK ACCK MPU interface RESET CS RD WR A0 ~ A4 D0 ~ D7 Others VCC GND TESTI, 0~6 TESTO Input Output Input Output Input Input Input Input Input Input/Output - - Input Output 3 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR DESCRIPTION OF ANALOG PIN FUNCTIONS (Cont.) Item Power supply Pin name AVCC DVCC GND AGND DGND Sensor signal AIN input part Gain control circuit C1, C2 LEVAJ Input/output - - - - Input Function Analog power supply pin (rated supply voltage: 5V) Digital power supply pin (rated supply voltage: 5V) Analog ground pin Digital ground pin Pin to input analog signals output from CCD or CIS (Signals from CCD are input through capacity coupling and those from CIS, with no clamping levels, are input directly.) Pin to control the frequency characteristic of the gain control circuit Pin to control the DC level of output signals of the gain control circuit. The output voltage, VGCAO, is obtained by the following equation: VGCAO = VLEVAJ + GV x VIN, where, VLEVAJ: voltage at LEVAJ VIN: input signal GV: gain of the gain control circuit VIN is the signal element corresponding to the signal level clamped through the input clamping circuit for CCD*CIS3 input or to the GND level for CIS1*CIS2 input. Signal output pin of the gain control circuit Signal input pin to the black clamping circuit. Use this with capacity coupling with the GCAO pin. Pin to set the black level clamping voltage. Sets the black level of signals output from the BCMO pin for CCD signal processing. Signal output pin of the black level clamping circuit Output of the circuit to generate the A/D full-scale point reference voltage (3.8V). Connected with VWL through the buffer inside the IC. To change the A/D reference voltage range, input a DC voltage from this pin. Output of the circuit to generate the A/D zero point reference voltage (1.8V). Connected with VBL through the buffer inside the IC. To change the A/D reference voltage range, input a DC voltage from this pin. Signal input pin to the A/D converting circuit. Use this by connecting with the BCMO pin for CCD or with the GCAO pin for CIS. Input signals in the voltage range (1.8V to 3.8V) set through VWL and VBL. Output of the circuit generating the A/D full-scale reference voltage (3.8V). Connected inside the IC with the A/D converter. Output of the circuit generating the A/D zero point reference voltage (1.8V). Connected inside the IC with the A/D converter. Input Input GCAO Black level clamping circuit BCMI BCMV Output Input Input BCMO A/D converter Vri+ Output Input Vri- Input ADIN Input VWL Output VBL Output 4 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (1) Operation mode The M66335 has three basic operations. Peak value detection: Adjusting the peak value of analog signals output from the analog circuit to the white reference voltage (VWL) of the A/D converter built in the M66335. Generation of data for uniformity correction: Generating data on a white reference original sheet for uniformity correction by the sensor unit and writing them to the memory for correction built in the M66335. Read: Reading original sheets, performing image processing of the read image data, and outputting in serial or parallel the indicated converted binary data. The M66335 is capable of performing the DMA transfer of multivalued data (6-bit data=D7~D2, D1=D0=0) after correction about uniformities. These three basic operations are performed in the following mode sequences for the CCD sensor and CIS sensor. The sensor is set through the register 00 (SENS). For the CIS sensor AGC mode The peak value of the 16 line cycle is detected by setting the AGC command in the register 00 at "H". To escape this mode, set the AGC command at "L" after a 20 line cycle (or a cycle of 16 lines or more) passed since the start. When this operation mode is started by the UNIF command after setting UMODE: "L" (black correction) in the register 00 and UNIFM: "H" (black and white correction) in the register 01, the system also generates black data for non-uniformity correction for black correction (for the 8 line cycle). To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. In the case of only white correction, the setting is not necessary. Follow the instruction below. When this operation mode is started by the UNIF command in the register 00 after setting UMODE: "H" (white correction) in the register 00 and UNIFM: "L" (only white correction) in the register 01, the system also generates white data for nonuniformity correction for white correction (for the 8 line cycle). To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. The reading operation is started by setting the SCAN command in the register 00 at "H". To escape this mode, set the SCAN mode at "L". The signal operations and data flow in each basic operation are shown in the page 4-217 and 4-218, and the flowchart is in the page 4-260 and 4-261. * * * UNIF mode (black) For the CCD sensor AGC mode The peak value of the 16 line cycle is detected by setting the AGC command in the register 00 at "H". To escape this mode, set the AGC command at "L" after a 20 line cycle (or a cycle of 16 lines or more) passed since the start. This operation mode is started by setting the UNIF command in the register 00 at "H" after setting UMODE: "H" (white correction) in the register 00 and UNIFM: "L" (only white correction) in the register 01. Starting by the UNIF command also makes the system generate data for nonuniformity correction for white correction (for the 8 line cycle). To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. The read operation mode is started by setting the SCAN command in the register 00 at "H". To escape this mode, set the SCAN command at "L". UNIF mode (white) UNIF mode (white) SCAN mode SCAN mode 5 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR OPERATIONS OF SIGNALS IN THE PEAK VALUE DETECTION OPERATION BCAO GCAO VWL,VBL ADIN Vri+,VriACCK SYSCK STIMB SCLK SVID Detection of background/ character levels correction table Error diffusion Selection of processing for conversion to binary Image bus interface Analog control Image processing sequence control signal 7bit A /D converter Image zone separation C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit AIN Uniformity correction Resolution change MTF compensation DMA control Organized dither MPU bus interface SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 FLOW OF DATA IN THE CREATION OF DATA FOR UNIFORMITY CORRECTION BCAO GCAO VWL,VBL ADIN Vri+,VriACCK SYSCK STIMB SCLK SVID Detection of background/ character levels correction table Error diffusion Selection of processing for conversion to binary Image bus interface Analog control Image processing sequence control signal 7bit A /D converter Image zone separation C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit AIN Uniformity correction Resolution change MTF compensation DMA control Organized dither MPU bus interface SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 6 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR FLOW OF DATA IN THE READING OPERATION (FOR OUTPUT IN SERIAL: BINARY DATA) BCAO GCAO Analog control VWL,VBL ADIN Vri+,VriImage processing sequence control signal 7bit A /D converter Image zone separation ACCK SYSCK STIMB SCLK SVID C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit Detection of background/ character levels g correction table Error diffusion AIN Uniformity correction Resolution change MTF compensation Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 : image data : correction or compensation data FLOW OF DATA IN THE READING OPERATION (FOR OUTPUT IN PARALLEL: BINARY DATA) BCAO GCAO Analog control VWL,VBL ADIN Vri+,VriImage processing sequence control signal 7bit A /D converter Image zone separation ACCK SYSCK STIMB SCLK SVID C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit Detection of background/ character levels g correction table Error diffusion AIN Uniformity correction Resolution change MTF compensation Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 : image data : correction or compensation data FLOW OF SIGNALS IN THE READING OPERATION (FOR MULTIVATED DATA) BCAO GCAO Analog control VWL,VBL ADIN Vri+,VriImage processing sequence control signal 7bit A /D converter Image zone separation ACCK SYSCK STIMB SCLK SVID C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit Detection of background/ character levels g correction table Error diffusion AIN Uniformity correction Resolution change MTF compensation Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 7 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (2) Line cycle and reading sequence The relationship between the line cycle and the reading sequence of the M66335 is shown in Fig. 1. The relationship between the CODEC interface operations and the reading sequence is shown in Fig. 2 and that between the DMA interface operations and the reading sequence is shown in Fig. 3. * Uniformity correction range (UNIFG): Defines the range where uniformity correction is performed. This range corresponds to the width of the sensor (B4 to A4). For the relationship between the sensor width and the uniformity correction range, see Table 2. * * AGC range (AGCG): Single-line cycle (1/ACCK): Defines the processing time per line of the M66335. The single-line cycle is decided by the line cycle counter value registers 03 and 04 (PRE_DATA), and the pixel transfer clock. The pixel transfer clock is 1/16 of SYSCK. 1 line cycle (1/ACCK) [NS] = line cycle counter value x pixel transfer clock cycle [NS] = (PRE_DATA + 1) x pixel transfer clock cycle [NS] = (PRE_DATA + 1) x 16/SYSCK [NS] After loading the PRE_DATA value, the line cycle counter generates the addresses of the following gate signals while counting down with the pixel transfer clock. Sensor start pulse (SH): Image sensor start pulse. The point of the start pulse is decided by the uniformity correction range (UNIFG) and the value of the register 05. [ST_PL] The ST_PL value must be set according to the following formulas for each image sensor type. CCD: ST_PL = dummy pixels of the sensor + 2 CIS: ST_PL = 2 Defines the range where peak value detection is performed. This range corresponds to the sensor width (B4 to A4). Auto gain control is performed for the whole width of the sensor (solid line) in the AGC mode and for the narrower width (dashed line) than the sensor width in the SCAN mode. For the relationship between the sensor width and the AGC range, see Table 2. * Original sheet reading width: Defines the reading width for original sheets. For original sheet widths narrower than the sensor width, the reading range (dashed line) is set, using the sensor center as the base center point. Therefore, the points for the original sheet should be based on the sensor center. For the relationship between the sensor width and the original sheet reading width, see Table 3. * * Pulse motor control signal (PTIM): Generates control signals for the pulse motor for the reading roller. PRE_DATA loading Countdown Line cycle (ACCK) Sensor start pulse (SH) ST_PL Uniformity correction range (UNIFG) AGC range (AGCG) 0 Relationship with the registers Registers 03 and 04 (PRE_DATA) Register 00 (SENS_W) Register 05 (ST_PL) Register 00 (SENS_W) Register 00 (SENS_W) Register 01 (SOURCE) Register 00 (SENS_W) Register 11, 12 (OFFSET) Original sheet reading range Pulse motor control (PTIM) 1 line cycle Fig. 1 Line cycle and the reading sequence 8 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ACCK SH SRDYB 1 2 3 4 5 Fig. 2 CODEC interface operations and the reading sequence (Binary data output : sirial output) ACCK SH 9 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Table 3 Original sheet reading widths according to the original sheet widths for the sensor widths A4 1943/215 3887/431 1943/215 3887/431 1584/564 3169/1129 A4 Original sheet width B4 Sensor width Resolution 200dpi 400dpi 200dpi 400dpi B4 2102/54 4206/110 2102/54 4206/110 1942/214 3886/430 A4 Table 2 Gate signal ranges for the sensor widths Sensor width Resolution Gate signal Uniformity correction range (UNIFG) AGC mode SCAN mode 200dpi 400dpi 200dpi 400dpi 200dpi 400dpi 2103/55 4207/111 2103/55 4207/111 2018/130 4037/261 B4 AGC range (AGCG) When original sheets narrower than the sensor width, cut out the original sheet width with the registers 11 to 14. (OFFSET, OUTLENGTH): (Region designation function) X/Y X : Left end address Y : Right end address X Y 10 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (3) Image processing function The M66335 converts image signals input from the image sensor into binary data. This includes the simple conversion of characters and the change of images with various densities into pseudo-halftone. Before the conversion, distortions and characteristic degradations which signals from the image sensor almost always have must be corrected or compensated. Image zone separation must also be performed to realize optimal conversion-to-binary of the image for the possible shortest transmission time. Functions required for image processing are as follows. Peak value detection Uniformity correction Resolution change (enlargement, reduction and averaging) MTF compensation correction Background/character level detection (simple conversion to binary) Change to pseudo-halftone Organized dither Error diffusion Image zone separation Designation of regions Peak value detection Because the A/D converter of the M66335 uses the input dynamic range at 2 Vp-p, the reference voltages (VWL, VBL) corresponding to the peak value are fixed. The peak value of analog signals output from the analog processing circuit must be detected before those signals are input to the A/D converter in order to adjust the analog signal peak value to the full-scale value of the converter. The peak value detection is performed by reading white data from the sensor in the AGC mode selected from its three modes (AGC, UNIF and SCAN) of the M66335. As shown in Fig. 4, preprocessing of peak value detection to increase the gain at the gain control is performed for a 8 line cycle and gain control processing to decrease the gain when the A/D converter overflows is performed for another 8 line cycle after the start command (register 00: AGC) in the AGC mode. As a result, the gain changes as shown in Fig. 5. * * * * * * * * * Peak value detection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Line cycle Preprocessing of peak value detection (increasing the gain) Fig. 4 Peak value detection Gain control on the peak value (decreasing the gain) Preprocessing of peak value detection After the completion of preprocessing of peak value detection VWL White data The output level of the last pixed of the line is adjusted to VWL. VBL One line Fig. 5 Changes of the gain in peak value detection VWL Gain control on the peak value After the completion of gain control on the peak value The peak value of the sensor output in the line is adjusted to VWL. VBL One line 11 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Uniformity correction Uniformity correction is to correct shading distortion due to less light at each end of the light source and faded light around the lens, or high frequency distortion due to characteristic variations pixel by pixel in the image sensor. As shown in Fig. 7, the M66335 makes blocks each of two pixels, creates a set of uniformity correction data for each block, and write them to the built-in correction memory (SRAM: 1024 word x 6 bits) in the UNIF mode selected from its three modes (AGC, UNIF and SCAN). The correction data created each for two pixels are read from the built-in correction memory to correct the input image data consecutively in the SCAN mode. With the register 01 (UNIFS) set at "1", the uniformity is not implemented. With the register 02 (RES) set at "1", uniformity correction is performed on a block for 4 pixels. For uniformity correction, white correction or the combination of black correction and white correction can be selected according to the types of image sensors as shown in Table 4. This is set in the register 00 (SENS, UMODE) and register 01 (UNIFM). To perform both black correction and white correction, the black correction must be done first. The M66335 implements the correction in the correction range of 50% as shown in Fig. 7. If a set of white correction data is beyond the correction range of 50%, the correction are not exactly performed as shown in Fig. 7. Therefore, ensure that input signals are within the range. Black level High frequency distortion Shading distortion White level 1 line Fig. 6 Waveform of white data output from the image sensor Table 4 Uniformity correction due to the image sensor Register Image Correcsensor tion CCD White correction White correction Creation of uniformity Selection of Type of the sensor correction data correction mode Register 00 (SENS) Register 00 (UMODE) Register 01 (UNIFM) 0 1 1 1 1 Period of black correction : 0 Period of white correction : 1 0 0 1 CIS Black correction White correction White correction + black correction Analog signal input VWL White data 27-1 VWL White correction Analog signal input White data 27-1 50% 26-1 50% 26-1 VBL Black data 1 line 0 VBL 0 1 line Correction on over-range data (in white correction) VWL Analog signal input White data 27-1 50% 26-1 White data over the correction range VBL 0 Section over the correction range 1 line Fig. 7 Uniformity correction 12 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR q Resolution change Resolution change is controlled through H/W in the horizontal scanning direction and through S/W in the vertical scanning direction. The sequence for resolution change is shown in Fig. 8. x In the case of reduction CNV_D indicates the current line read. "0": 1 line of data are output. "1": No line of data are output. Horizontal scanning direction The scaling factor is written from the register 15 (CNV_D) to the built-in resolution change memory (100W x 1 bit) bit by bit by 100 operations. MSSEL of the register 6 must be set at "0" (which specifies the horizontal scanning direction) before the scaling factor is written in the memory. The procedure to specify CNV_D is as follows. x In the case of enlargement CNV_D indicates the next line read. "0": 1 line of data are output with PTIM generated (paper driven). "1": 1 line of data are output with PTIM generated (paper not driven). (Paper not driven: the same line is read again.) x In the case of reduction Resolution change Enlargement/reduction Specifying enlargement/reduction is set in CONVX/CONVY. for horizontal/vertical scanning MSSEL is set at 0. Specifying horizontal scanning Data written in the resolution change memory have the following meaning. "0": 1 pixel is output. "1": No pixel is output. (Example of reduction to 75%) 75 0's and 25 1's are written in the memory. The intervals of 1's should be as equal as possible to obtain the image with better quality. x In the case of enlargement Data setting in CNV_D Setting the scaling factor for resolution change in the (100 bits in quantity) horizontal scanning direction MSSEL is set at 1. Specifying vertical scanning Data written in the resolution change memory have the following meaning. "0": 1 pixel is output. "1": 2 pixels are output. (Example of enlargement to 150%) 50 0's and 50 1's are written in the memory. The intervals of 1's should be as equal as possible to obtain the image with better quality as in the reduction. NO Setting the scaling factor for Data setting in CNV_D resolution change in the vertical (1 bit in quantity) scanning direction Setting of SRDY Start of reading a single line Vertical scanning direction Processing of lines to implement the scaling factor in the vertical scanning direction is decided for each line through the register. MSSEL of the register 6 must be set at "1" (which specifies the vertical scanning direction), and either "0" or "1" written in the register 15 (CNV_D) before the processing of each line. The timing for this setting is in the period between the first transition of the INT signal (synchronized with that of ACCK) and that of the SH signal (the start of taking the SRDY signal in). The procedure to specify CNV_D is as follows. NO INT generated? YES Page end? YES END End of reading a single line Fig. 8 Sequence of resolution change setting 13 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Use the PTIMB signal as control signals for the pulse motor for the reading roller. The sequence for reduction is shown in Fig. 9 and that ACCK SH for enlargement in Fig. 10. Reduced line Reduced line 1 0 1 0 1 At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting mode for enlargement/reduction in vertical scanning, the first line is set. 2 With a flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: `H') 3 With a flow of SH, SRDYB: `L' is taken in, when scanning starts and PTIMB is output. (SSCAN: `H') 4 During the period that STIMB is at `L', converted binary data are output while the data for reduced lines are not output because STIMB for them are at `H'. 5 With a flow of ACCK, SRDYB: `H' is taken in, when the reading of the single line is completed. (SSCAN: `L') 6 With a flow of SSCAN, INT is asserted. (INT: `H') 7 With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is negated; and then SRDYB is set at `L'. : Output section Fig. 9 Reduction processing sequence ACCK SH 1 At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting mode for enlargement/reduction in vertical scanning, the first line is set. 2 With a flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: `H') 3 With a flow of SH, SRDYB: `L' is taken in, when scanning starts and PTIMB is output while it is not output for enlarged lines. (SSCAN: `H') 4 During the period that STIMB is at `L', converted binary data are output. 5 With a flow of ACCK, SRDYB: `H' is taken in, when the reading of the single line is completed. (SSCAN: `L') 6 With a flow of SSCAN, INT is asserted. (INT: `H') 7 With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is negated; and then SRDYB is set at `L'. Fig. 10 Enlargement processing sequence 14 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR MTF compensation As shown in Fig. 11, image data of characters or pictures photoelectrically converted by the sensor unit show degradation in resolution. MTF compensation function of the M66335 restores the resolution of those data and expands the apparent dynamic range by strengthening the high-pass frequency constituent with the Laplacian filter. Photoelectric conversion Photoelectric conversion Original (character) Image signal MTF compensation Data after compensation Photoelectric conversion Original (photo) Image signal MTF compensation Data after compensation Resolution compensation X = X + ((X - A) + (X - B) + (X - C) + (X - D)) where, : MTF compensation coefficient in the register 08 (MTF_C, MTF_I) In the above equation, is set according to the register 07 : MODE (selection of conversion-into-binary mode) as follows: MODE : 00 (simple binary) = MTF_C MODE : 01 (organized dither) = MTF_I MODE : 10 (image zone separation) separation (character) = MTF_C for image zone separation (photo) = MTF_I for image zone MODE : 11 (error diffusion) = MTF_I Fig. 11 MTF compensation 15 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR correction correction according to the sensitivity characteristics (logarithmic characteristics) of human eyes is implemented to approximate the image data to natural images. To do this, the M66335 writes the correction table to the built-in SRAM and read the corrected values corresponding to read image data values from the SRAM. = 0.45 is considered to be the optimal for correction for thermal head printers. Fig. 12 shows a characteristics example at = 0.45. correction processing is set through the register 06 : GAMMA as follows. =1 = conversion table value = 1 for image zone separation (character) = conversion table value for image zone separation (photo) GAMMA : 11 = conversion table value for image zone separation (character) = 1 for image zone separation (photo) For the procedures of inputting/outputting of data, refer to the section on writing to/reading from the correction memory. GAMMA : 00 GAMMA : 01 GAMMA : 10 6 Image data A <5,0> DO <5,0> (Address) (Output) correction memory 6 Data after correction 1.0 White 63 56 Image data after correction (memory output) DOUT 47 = 0.45 34 25 =1 0 Dlow DIN Dup 1.0 IF(DIN < Dlow) DOUT = 0 Black 0 Black : 0 8 16 32 Image data (address) 48 White : 63 IF(Dlow DIN < Dup) DOUT = DIN-Dlow Dup-Dlow ( ) Fig. 12 correction by means of the conversion table IF(Dup DIN) DOUT = 1.0 16 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Background/character level detection The M66335 uses not the fixed threshold system but the floating threshold system, where the optimal threshold for simple conversionto-binary of objective pixels are continually generated by constantly detecting background/character levels. Accordingly, the threshold value proper for image data is generated without processing the data. The threshold value is used for the areas to be converted to binary when simple conversion-to-binary or image zone separation is selected as the mode of conversion to binary in reading data. : register 07 (MODE) Background level counter When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to the data. When image data smaller (darker in light) than the current value are input, this counter counts down to approximate to the data. Setting of the rate of count-up/count-down following data input : register 0C (MAX_UP, MAX_DOWN) Setting of the lowest limit for background levels : register 0E (LL_MAX) Character level counter When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to the data. When image data smaller (darker in light) than the current value are input, this counter counts down to approximate to the data. Setting of the rate of count-down following data input : register 0C (MIN_UP) Setting of the highest limit for character levels : register 0D (UL_MIN) Image data Background level detection counter Generation of the threshold value Character level detection counter Comparison Converted binary data This slope is decided through MAX_UP. This slope is decided through MAX_DOWN. Fixing of the background level White level Background level Lowest limit of the background level (LL_MAX) Input data Threshold level Character level Highest limit of the character level (UL_MIN) Black level This slope is decided through MIN_UP. Fixing of the character level Threshold level = (background level point - character level) x K + character level K = threshold factor for conversion to binary: register 07 (SLICE) Lowest limit of the background level (LL_MAX) > highest limit of the character level (UL_MIN) Fig. 13 Background/character levels 17 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Error diffusion The error diffusion, which is a conditional determination method, locally diffuses density errors between the original image and the result to obtain the best approximation. This generates images with good compatibility of gradation and resolution. This is operated by selecting the error diffusion in conversion-intobinary mode selection. : register 07 (MODE) In error diffusion, dithers as well as density errors are added to image data. The dithers are data as commonly used for the dither matrix. : register 08 (ERROR) correction must be performed in the error diffusion. * Organized dither The M66335 has built-in SRAM with a configuration of 64 words x 6 bits for organized dither memory. In the initial setting, write the threshold value proper for the preferred dither pattern to the dither memory after setting the dither matrix size. : register 07 (DITH) : register 10 (DITH_D) An example of dither patterns is shown in Fig. xx. For the procedure of inputting/outputting data, refer to the section on writing to/reading from the dither memory. Dither matrix -32 m 17 10 2 n Integrated error klEm-k, n-1 (Note 2) K1 9 11 5 n 12 8 20 15 25 19 Fmn K2 Fmn Gmn m +- Fmn > 32 Gmn = 63 (white) Fmn < 32 Gmn = 0 (black) Weighting of the error filter kl 1 2 2 4 4 2 1 Error Emn = Fmn - Gmn (Note 1) Error buffer memory Preceding line Current line Note 1: Characterized by using the difference from the corrected value Fmn rather than that from the original pixel Fmn. 2: Errors before the point of remark are integrated. Fmn = Fmn + K1 (1/kl) klEm-k, n-1 + K2 (dither -32) k,1 k,1 K1 = register 08 (error) K2 = register 08 (dither addition factor) Fig. 14 Error diffusion method 18 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Image zone separation To make data conversion fit for each image zone, a black and white image is separated into the zones to be converted to binary and the gradation zones. The binary zone is processed through simple conversion to binary and the gradation zone through the error diffusion. : register 08 to 0E In the black and white image, each window of the gradation zone (photo) does not have a large difference of luminance in it. With this characteristic of the gradation zone, it is distinguished from the conversion-into-binary zone through the following method. Lmax: maximum illumination in window Lmin : minimum illumination in window Determining inequality 1: Lmax - Lmin>A (because the zone to be converted to binary has a large difference in luminance in it.): register 09 Difference (SEPA_A) Determining inequality 2: Lmin>B (for the wholly white area): register 0A Minimum (SEPA_B) Determining inequality 3: Lmax Difference Lmax Minimum Lm i n Maximum A Input data Lm i n Black level = 0 Lmax-Lm i n Fig. 15 Image zone separation B C Lmax 19 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Region designation function The sensor width is fixed for A4 and B4. The region designation function is to output only the data for a region defined and designated in terms of output data after resolution change (or after uniformity correction for multivalued data). Registers 11 to 14 (OFFSET, OUTLENGTH) Output width Designated region OFFSET OUTLENGTH Fig. 16 Cut-out function 20 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (4) CODEC interface (Binary data output) Serial output SRDYB SH A STIMB 10 (Equal scale, reduced scale) SCLK 2 10 2 4 12 B SVID 4 (Enlarged scale) SCLK 2 2 2 4 4 4 SVID Unit : 1/SYSCK Note: A is decided through the registers 05 (ST_PL) 11 and 12 (OFFSET), and B through the registers 13 and 14 (OUTLENGTH). Parallel output Pixel SCLK SVID DRQ DAK RD D0 D1 D2 D3 D4 D5 D6 D7 N-1 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 1 2 3 4 5 6 7 8 N-2 N-3 N-4 N-5 N-6 N-7 N-8 Note: The 3-line handshake of SRDY, SH and STIM, which is the interface with CODEC, is the same as serial output. 21 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (5) DMA interface (multivalued output) The DMA transfer of data after non-uniformity correction can be performed by setting P_O) of the register 01: at "1" (existence of DMA output) and M_B of that register at "1" (multivalue). With this setting, neither enlargement, nor reduction, nor 400 dpi of resolution can be set. SSCAN DRQ 2 (DMA counter reset signal) DAKB 1 4 RDB 3 (DMA counter signal) (DMAFIN) 5 INT D<7 : 2> 6 (XXXX): internal signal On completion of reading one line, with a flow of SSCAN, the reset signal is entered in the DMA counter. With a flow of the reset signal, DRQ shifts to `H', when the DMA transfer becomes ready. With DAKB at `L' and a flow of RDB, DRQ shifts to `L', when multivalued data are output to D <7 : 2> during the period that RDB is at `L'. With a flow of DAKB, the DMA counter counts up and DRQ shifts to `H', when the DMA transfer becomes ready again. The cycle of the above 3 and 4 is repeated until the DMA counter counts up to reach the number of output pixels set in the registers 13 and 14 OUTLENGTH subtracted by one. By that repetitive operation, DMAFIN shifts to `H' to terminate the DMA transfer when it reaches the set number. 6 With a flow of DMAFIN, INT shifts to `H', when CPU has an interrupt. 7 Reading is resumed from the next line by negating the INT signal through the register 17 (INTCLR). 1 2 3 4 5 22 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (6) Writing to/reading from the dither memory, correction memory, uniformity correction memory, and resolution change memory The sequences of writing a dither pattern to and reading it from SRAM with a configuration of 64 words x 6 bits which is built in the M66335 Writing to the dither memory (MPU M66335) Initial setting (1) CSB A4 ~ A0 Initial setting (2) Memory address (0) Memory address (1) for organized dither are shown below. 07H 01H 10H 10H ~ WRB D7 ~ D0 (Input) D6,D5 1 Reading from the dither memory (M66335 MPU) Initial setting (1) CSB A4 ~ A0 Initial setting (2) Memory address (0) Memory address (1) D0="1" 2 DATA (0) 3 DATA (1) 3 07H 01H 10H 10H ~ WRB D7 ~ D0 (Input) RDB D7 ~ D0 (Output) 1 2 D6,D5 D0="1" DATA (0) 4 DATA (1) 4 1 D6 and D5 (DITH) of the register 07 are set to define the dither matrix size. 2 D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the dither memory. 3 DITH_D is selected in the register 10, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the dither memory is incremented at the edge of the first transition of WR. (For writing) 4 DITH_D is selected in the register 10, and DATA (0) of the dither memory is read into the MPU bus (D5 to D0). The address counter of the dither memory is incremented at the edge of the first transition of RD. (For reading) Dither matrix addresses A0 A4 A8 A1 A5 A9 A2 A6 A3 A7 A10 A11 A12 A13 A14 A15 4 x 4 matrix A0 A4 A8 A12 A16 A20 A24 A28 A1 A2 A3 A5 A6 A7 A9 A10 A11 A13 A14 A15 A17 A18 A19 A21 A22 A23 A25 A26 A27 A29 A30 A31 4 x 8 matrix A0 A8 A16 A24 A32 A40 A48 A56 A1 A9 A17 A25 A33 A41 A49 A57 A2 A3 A4 A5 A10 A11 A12 A13 A18 A19 A20 A21 A26 A27 A28 A29 A34 A35 A36 A37 A42 A43 A44 A45 A50 A51 A52 A53 A58 A59 A60 A61 8 x 8 matrix A6 A14 A22 A33 A38 A46 A54 A62 A7 A15 A23 A31 A39 A47 A55 A63 23 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR The sequences of writing correction table to and reading it from SRAM with a configuration of 64 words x 6 bits which is built in the M66335 for correction are shown below. Writing to the correction memory (MPU M66335) Initial setting (1) CSB A4 ~ A0 Memory address (0) Memory address (1) 01H 0FH 0FH ~ WRB D7 ~ D0 (Input) D0="1" 1 Reading from the correction memory (M66335 MPU) Initial setting (2) CSB A4 ~ A0 Memory address (0) Memory address (1) DATA (0) 2 DATA (1) 2 01H 0FH 0FH ~ WRB D7 ~ D0 (Input) RDB D7 ~ D0 (Output) 1 D0="1" DATA (0) 3 DATA (1) 3 1 D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the correction memory. 2 GAMMA_D is selected in the register 0F, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the correction memory is incremented at the edge of the first transition of WRB. (For writing) 3 GAMMA_D is selected in the register 0F, and DATA (0) of the correction memory is read into the MPU bus (D5 to D0). The address counter of the correction memory is incremented at the edge of the first transition of RDB. (For reading) 24 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Uniformity correction data can be written to and read from SRAM for uniformity correction built in the M66335 through the MPU bus. With this operation, the uniformity data can be temporarily saved in the Writing to the uniformity correction memory (MPU M66335) Initial setting (1) CSB A4 ~ A0 00H 01H Initial setting (2) backup memory when the power is off. The sequences of writing and reading uniformity correction data are shown below. Memory address (0) Memory address (1) 19H 19H ~ WRB D7 ~ D0 (Input) D1 1 D0="1" 2 DATA (0) 3 DATA (1) 3 Reading from the uniformity correction memory (M66335 MPU) Initial setting (1) CSB A4 ~ A0 00H 01H 19H Initial setting (2) Memory address (0) Memory address (1) 19H ~ WRB D7 ~ D0 (Input) RDB D7 ~ D0 (Output) 1 2 D1 D0="1" DATA (0) 4 DATA (1) 4 1 "0" (black correction) or "1" (white correction) is set in D1 (Umode) of the register 00. 2 D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the uniformity correction memory. 3 UNIF_D is selected in the register 19, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the uniformity correction memory is incremented at the edge of the first transition of WRB. (For writing) 4 UNIF_D is selected in the register 19, and DATA (0) of the uniformity correction memory is read into the MPU bus (D5 to D0). The address counter of the uniformity correction memory is incremented at the edge of the first transition of RDB. (For reading) 25 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR The sequences of writing a resolution change table to and reading it from SRAM with a configuration of 100 words x 1 bit which is built in the M66335 for resolution change are shown below. Writing to the resolution change memory (MPU M66335) Initial setting (1) CSB A4 ~ A0 06H 01H 15H Initial setting (2) Memory address (0) Memory address (1) 15H ~ WRB D7 ~ D0 (Input) D7="0" 1 D0="1" 2 DATA (0) 3 DATA (1) 3 Reading from the resolution change memory (M66335 MPU) Initial setting (1) CSB A4 ~ A0 06H 01H 15H Initial setting (2) Memory address (0) Memory address (1) 15H ~ WRB D7 ~ D0 (Input) RDB D7 ~ D0 (Output) 1 2 D7="0" D0="1" DATA (0) 4 DATA (1) 4 1 "0" (horizontal scan) is set in D7 (MSSEL) of the register 06. 2 D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the resolution change memory. 3 CNV_D is selected in the register 15, and DATA (0) of the MPU bus (D0) is written in the memory. The address counter of the resolution change memory is incremented at the edge of the first transition of WRB. (For writing) 4 CNV_D is selected in the register 15, and DATA (0) of the resolution change memory is read into the MPU bus (D0). The address counter of the resolution change memory is incremented at the edge of the first transition of RDB. (For reading) 26 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR List of the M66335FP registers R/W R/W R/W W W W W W W W W W W W W W R/W R/W W W W W W R/W W R/W R/W A4 ~ A0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H Default 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 1FH 20H - - 00H 00H 00H 00H - 00H - 00H 00H INTCLR GAIN <7 : 0> UNIF_D <5 : 0> AGCSTP SRDYS MAX_UP <1 : 0> MSSEL POL AVE D7 RESET SOURCE RES D6 SENS S/H_W LCMPS D5 SENS_W SH_W BLS D4 AGC UNIFS BLCMPS D3 UNIF P_O CCD D2 SCAN M_B CIS3 D1 UMODE UNIFM CIS2 D0 "L" CNTRST CIS1 PRE_DATA (7 : 0) PRE_DATA (13 : 8) ST_PL (7 : 0) CONVX <1 : 0> CONVY <1 : 0> GAMMA <1 : 0> SLICE <2 : 0> MTF_I <1 : 0> DITH <1 : 0> MODE <1 : 0> MTF_C <1 : 0> SEPA_A (5 : 0) SEPA_B (5 : 0) SEPA_C (5 : 0) MAX_DOWN <1 : 0> UL_MIN <5 : 0> LL_MAX <5 : 0> GAMMA_D (5 : 0) DITH_D (5 : 0) OFFSET <7 : 0> ERROR <1 : 0> MIN_UP <1 : 0> OFFSET <12 : 8> OUTLENGTH <7 : 0> OUTLENGTH <12 : 8> CNV_D SRDYB 27 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Register structure Address 00H R/W R/W D7 RESET D6 SENS D5 SENS_W D4 AGC D3 UNIF Description D2 SCAN D1 UMODE D0 "L" (Default value: 00H) D7 0 1 RESET : system reset Normal mode Reset mode q With D7 = 1, the system is reset during the period that the write pulse is "L". () Write only D6 0 1 SENS : sensor type CCD CIS: (75% of clock duty) D5 0 1 SENS_W : reading width of the sensor A4 B4 D4 0 1 AGC : AGC mode Stop Start q Controls start/stop of the AGC mode. D3 0 1 UNIF : UNIF mode Stop Start q Controls start/stop of the UNIF mode. D2 0 1 SCAN : SCAN mode Stop Start q Controls start/stop of the SCAN mode. D1 0 1 UMODE : uniformity correction in the UNIF mode Black correction + white correction Black correction White correction Only white correction - White correction 01H R/W D7 SOURCE D6 S/H_W D5 SH_W D4 UNIFS D3 P_O D2 M_B D1 UNIFM D0 CNTRST (Default value : 00H) D7 0 1 SOURCE : reading width of the original A4 B4 D6 0 1 S/H_W : S/W pulse width Normal (quadruple the system clock cycle) Normal multiplied by 0.5 28 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 01H R/W R/W D5 0 1 SH_W : SH pulse width Normal (16 times the system clock cycle) Reverse of normal multiplied by 2 Description D4 0 1 UNIFS : uniformity correction Valid Invalid D3 0 1 P_O : DMA output Without DMA output With DMA output q D0 is output in the form of LSB and D7 in the form of MSB. D2 0 1 M_B : processing mode Binary Multivalue q With the multivalue selected, data (6 bit) after nonuniformity correction can be output through the DMA transfer. D1 0 1 D0 0 1 02H W D7 RES UNIF : uniformity correction in SCAN White correction Black correction + white correction CNTRST : address counter reset Normal mode Reset mode D6 LCMPS D5 BLS D4 BLCMPS D3 CCD q q With D0 = 1, the counter is reset during the period that the write pulse is "L". All the built-in RAM addresses are reset. () Write only D2 CIS3 D1 CIS2 D0 CIS1 (Default value : 00H) D7 0 1 D5 0 1 D4 0 1 RES : resolution 200dpi 400dpi BLS : bit clamping Invalid Valid BLCMPS : black level line clamping Invalid Valid D6 0 1 LCMPS : line clamping Invalid Valid D3 0 0 0 1 D2 0 0 1 0 D1 0 1 0 0 D0 1 0 0 0 Sensors compatible with image sensor interfaces CIS1 : sensors with the input level of 2V or higher CIS2 : sensors with the input level of under 2V CIS3 : sensors capable of line clamping CCD 29 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 03H R/W W D7 D6 D5 D4 D3 Description D2 D1 D0 (Default value : 00H) PRE_DATA <7 : 0> D7 to D0 : PRE_DATA <7 : 0> the lowest order 8 bits of the single-line cycle counter value 04H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) PRE_DATA <13 : 8> D5 to D0 : PRE_DATA <13 : 8> the highest order 6 bits of the single-line cycle counter value 05H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) ST_PL <7 : 0> D7 to D0 : ST_PL <7 : 0> start pulse position to the sensor q Set ST_PL = (dummy pixels of the sensor + 2). 06H W D7 MSSEL D6 AVE D5 D4 D3 D2 D1 D0 (Default value : 00H) CONVX CONVY GAMMA D7 0 1 MSSEL : horizontal and vertical setting Horizontal Vertical D6 0 1 AVE : averaging processing With averaging Without averaging q When "with averaging" selected : For enlargement : inserted lines are the average of the preceding one and the current one; and For reduction : the subsequent lines from removed lines are the average of the removed one and the current one. q D5 0 0 1 1 D4 0 1 0 1 CONVX : enlargement/reduction mode in the horizontal scanning direction Original scale Enlargement Reduction RES = 1 With the setting of 400dpi, enlargement cannot be set. D3 0 0 1 1 D2 0 1 0 1 CONVY : enlargement/reduction mode in the horizontal scanning direction Original scale Enlargement Reduction 30 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 06H R/W W D1 0 0 1 1 D0 0 1 0 1 Description GAMMA : correction processing Character, photo : = 1 Character, photo : = download value Character : = 1; photo : = download value Character : = download value ; photo : = 1 Note: Judgment between character and photo is based on the result of image zone separation. 07H W D7 POL D6 DITH D5 D4 MODE D3 D2 D1 SLICE D0 (Default value : 00H) D7 0 1 POL : conversion-to-binary output mode White : 1; black : 0 White : 0; black : 1 D6 0 0 1 1 D5 0 1 0 1 DITH : dither matrix size 4x4 4x8 8x8 - D4 0 0 1 1 D3 0 1 0 1 MODE : selection of the conversion-to-binary mode Simple binary Organized dither Image zone separation (simple binary + error diffusion) Error diffusion D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 SLICE : threshold factor for conversion to binary 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 31 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 08H R/W W D7 D6 D5 D4 D3 Description D2 MTF_C D1 MTF_I D0 (Default value : 00H) ERROR D5 0 0 1 1 D4 0 1 0 1 ERROR Error (base) Strong (7/8) Strong (7/8) Weak (3/4) Weak (3/4) Rate of dither addition to errors Weak (1/8) Strong (1/4) Weak (1/8) Strong (1/4) D3 0 0 1 1 D2 0 1 0 1 MTF_C : MTF compensation factor 1/4 1/2 1 0 Note: This is valid when MODE is simple binary or image zone separation (character). D1 0 0 1 1 D0 0 1 0 1 MTF_I : MTF compensation factor 1/4 1/2 1 0 Note: This is valid when MODE is organized dither, error diffusion or image zone separation (photo). 09H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) SEPA_A D5 to D0 : SEPA_A Image zone separation parameter (differential) 0AH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) SEPA_B D5 to D0 : SEPA_B Image zone separation parameter (minimum) 0BH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) SEPA_C D5 to D0 : SEPA_C Image zone separation parameter (maximum) 32 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 0CH R/W W D7 D6 D5 D4 D3 Description D2 D1 D0 (Default value : 00H) MAX_UP MAX_DOWN MIN_UP D5 0 0 1 1 D4 0 1 0 1 MAX_UP : background level detection Clock for the up counter Ordinary (T = (single pixel cycle) x 32) Slow (T = (single pixel cycle) x 64) Fast (T = (single pixel cycle) x 16) Fastest (T = (single pixel cycle) x 8) D3 0 0 1 1 D2 0 1 0 1 MAX_DOWN : background level detection Clock for the down counter Ordinary (T = (single pixel cycle) x 128) Slow (T = (single pixel cycle) x 256) Fast (T = (single pixel cycle) x 64) Fastest (T = (single pixel cycle) x 32) D1 0 0 1 1 0DH W D7 D0 0 1 0 1 MIN_UP : character level detection Clock for the up counter Ordinary (T = (single pixel cycle) x 128) Slow (T = (single pixel cycle) x 256) Fast (T = (single pixel cycle) x 64) Fastest (T = (single pixel cycle) x 32) D6 D5 D4 D3 D2 D1 D0 (Default value : 1FH) UL_MIN D5 to D0 : UL_MIN Detection of background/character levels Highest limit of character levels 0EH W D7 D6 D5 D4 D3 D2 D1 D0 LL_MAX D5 to D0 : LL_MAX Detection of background/character levels Lowest limit of background levels Lowest limit of background levels (LL_MAX) > highest limit of character levels (UL_MIN) 0FH R/W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 20H) GAMMA_D <5 : 0> D5 to D0 : GAMMA_D Built-in memory data 10H R/W D7 D6 D5 D4 D3 D2 D1 D0 DITH_D <5 : 0> D5 to D0 : DITH_D Built-in dither memory data 33 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 11H R/W W D7 D6 D5 D4 D3 Description D2 D1 D0 (Default value : 00H) OFFSET <7 : 0> D7 to D0 : OFFSET <7 : 0> Offset for cut-out Lowest order 8 bits 12H W D7 D6 D5 D4 D3 D2 OFFSET <12 : 8> D1 D0 (Default value : 00H) D3 to D0 : OFFSET <12 : 8> Offset for cut-out Highest order 5 bits 13H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) OUTLENGTH <7 : 0> D7 to D0 : OUTLENGTH <7 : 0> No. of output pixels Lowest order 8 bits 14H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) OUTLENGTH <12 : 8> D3 to D0 : OUTLENGTH <12 : 8> No. of output pixels Highest order 5 bits Note: OUTLENGTH <12 : 8> must be a multiple of 8. If a number of output pixels is not a multiple of 8, the remainder of the division must be omitted. 15H R/W D7 D6 D5 D4 D3 D2 D1 D0 CNV_D D0 : CNV_D Indication of enlargement/reduction 34 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Address 16H R/W R/W D7 D6 D5 D4 D3 Description D2 D1 D0 SRDYB (Default value : 00H) AGCSTP SRDYS D2 0 1 AGCSTP : gain control counter Gain control counter valid. Gain fixed. D1 0 1 SRDYS : SRDY control SRDY control through the register SRDY control through the external pin D0 0 1 17H W D7 SRDYB : data transfer start ready. Transfer allowed. Transfer not allowed. q In the case of data control through the register, the SDRYB input pin must be always set at "H". For the control through the register, the SRDY register must be controlled line by line. ( ) Write only D6 D5 D4 D3 D2 D1 D0 INTCLR INT signals are negated by accessing to this address. 18H R/W D7 D6 D5 D4 D3 D2 D1 D0 GAIN <7 : 0> In reading : the current gain value of the gain control counter can be read. In writing : the gain value of the gain control counter can be set. However, this is valid only if AGCSTP = 1. 19H R/W D7 D6 D5 D4 D3 D2 D1 D0 q UNIF <5 : 0> With UMODE = 0, access to the uniformity correction memory for black correction is available. With UMODE = 1, access to the uniformity correction memory for white correction is available. q D5 to D0 : UNIF_D Built- in uniformity correction memory data 35 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Description of the Operations of the Analog Circuits The configuration of the analog processing circuits is shown in Fig. 17. (1) Sensor selection circuit The four types of sensors in the table can be connected to the circuit. Register 02H CCD CIS1 CIS2 CIS3 Sensor type CCD sensor CIS sensor which outputs light voltages (white voltage) of 3.5V or lower CIS sensor which outputs light voltages (white voltage) of 2V or lower CIS sensor which output shielding pixels for each line Black Max.500mVpp. White Blanking element Signaling element The amplitudes of sensor signals are multiplied by -4 through the two operating amplifiers directly after the switch to select the CCD mode. (The waveforms of the signals are inverted at the same time.) As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2V. Shielding pixel part Effective pixel part White Max.3.5V Black 200mV Signaling element The amplitude of signals input from the sensor are halved. Then, their reference potential is shifted up to 2.2V. As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2V. White Max.2V Black 200mV Signaling element The reference potential of signals input from the sensor is shifted up to 2.2V. As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2V. White 2Vpp. Black Clamping level Shielding pixel part Signaling element Effective pixel part Sensor signals with a dark voltage of 2.2V clamped by line clamping input are directly input to the sample and hold circuit. 36 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR (2) Line clamping circuit This circuit is used for CCD (line clamping mode) and CIS3. The reference voltage (dark voltage) output in the shielding pixel part of the sensor is sampled by LCMP (line clamping pulses) and shifted up to the internal reference voltage of 2.2V. This is not used for the CIS1 or CIS2 input sensor (set off constantly). : register 02 (LCMPS) (6) Black level clamping circuit This circuit adjust the level of reference voltage to the A/D converter from analog circuits. The black clamping circuit is used in the CCD or CID3 mode. (See Figs. 18, 19 and 22) The GCAO pin and the BCMI pin are capacitycoupled. The output reference potential in the shielding pixel part of sensor signals are applied to the BCMV pin as the VBL (black level reference voltage of 1.8V) for the A/D converter. BLCMP (black level clamping pulses) are generated concurrently with the shielding pixel part of each line. To turn off this circuit, set BLCMPS invalid and apply the black level reference voltage of the A/D converter to the BCMV pin. : register 02 (BLCMPS) In the CIS1 or CIS2 mode, the LEVAJ pin is used. (See Figs. 20 and 21) Voltage is applied to the LEVAJ pin so that the reference potential of output at the GCAO pin can be adjusted to the VBL (black level reference voltage of 1.8V) of the A/D converter. Set voltage input to the LEVAJ pin as follows. VLEVAJ = VVBL - A x GV + 0.2 [V] VGCAO = VLEVAJ + GV x VIN [V] where, A: the lowest limit of dark voltage of the sensor [V] GV: gain (multiplying factor) of the gain control circuit VIN: signals input from the sensor [V] (3) Sample and hold circuit and bit clamping circuit In the CCD mode, bit clamping, as well as line clamping, can be performed. The blanking elements of each pixel of sensor output is sampled by BTCMP (bit clamping pulses). The differences of signals from the reference potential sampled by the bit clamping circuit are input to the gain control circuit of next step as signaling elements. To turn off bit clamping, set BLS invalid, so that the reference potential will be fixed at the internal reference potential of 2.2V. : register 02 (BLS) (4) Gain control circuit The amplifying factor (gain) must be adjusted so that the amplitudes of sensor signals can come within the dynamic range of the A/D converter. The gain is set through the automatic gain control in the AGC mode (register 00) or directly through the register 18 (GAIN <7 : 0>). The gain changes within the following ranges according to the sensor used. Mode CCD CIS1 CIS2 CIS3 Amplifying factor of signals (gain) 4 to 20 0.5 to 2.5 1 to 5 1 to 5 In the AGC mode, the gain control counter is set at the greatest gain in the initial state and then counted down each time an overflow bit is output from the A/D converter. The count (gain) of the gain control counter is directly read/written through the register 18 (GAIN <7 : 0>). The counting operation of the counter can be controlled through the register 16 (AGCSTP). (5) Internal reference voltage Internal reference voltage source for the analog circuits: this generates the reference voltage (2.2V) for the line clamping circuit, the sample and hold circuit, and the bit clamping circuit. A/D converter reference voltage generation circuit: this generates VWL (white level reference voltage of 3.8V) and VBL (black level reference voltage of 1.8V) for the A/D converter. 37 38 C1C2 GCAO LEVAJ BCMV BCMI BCMO VCC S/H BTCMPBLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sample and hold circuit - + + - - + AVCC DVCC VCC AVDD MCIS<3:1>,MCCD + - MCIS1 AIN GCA + - - + - + - + AIN Level shift circuit(2.2V) MCIS2 MCIS3 8 Bit clamping circuit AGCSEL <7:0> 2.2V - + LCMP Black level clamping circuit - + - + Gain control circuit Fig. 17 Circuit Configuration of the Analog Part of the M66335FP LCMP MCIS<3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN<7:0> Reference voltage generating circuit for the A/D converter + - + - MCCD Input clamping circuit Digital circuit Internal reference voltage source for the analog circuits VriAVCC DVCC OF DIN<6:0> Vref- Vri+ Vref+ AGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET 1.8V 3.8V AGND VriVVBL=1.8 [V] Vri+ VBL VWL ADIN DGND GND FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI DIGITAL ASSP M66335FP AGND DGND GND MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CCD MODE/BIT CLAMPING) Register Address Bit Mode Signal Setting 00H D6 SENS D6 LCMPS D5 BLS D4 BLCMPS 02H D3 CCD D2 CIS3 D1 CIS2 D0 CIS1 CCD (bit clamping) 1 1 Shielding pixel part 1 1 1 0 0 0 Non-signaling part Effective pixel part SH CK1 CCD signal output LCMP BTCMP S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Non-signaling part 2 2 12 16 Shielding pixel part Effective pixel part Unit : 1/SYSCK SH CK1 CCD signal output N 16 3 4 9 LCMP 16 BTCMP S/H 16 34 13 2 9 1 GCAO signal output BLCMP N 8 8 BCMO signal output A/D clock A/D output N N 39 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CCD MODE/LINE CLAMPING) Register Address Bit Mode Signal Setting 00H D6 SENS D6 LCMPS D5 BLS D4 BLCMPS 02H D3 CCD D2 CIS3 D1 CIS2 D0 CIS1 CCD (line clamping) 1 1 Shielding pixel part 0 1 1 Effective pixel part 0 0 0 Non-signaling part SH CK1 CCD signal output LCMP BTCMP="H" S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Non-signaling part Shielding pixel part Effective pixel part Unit : 1/SYSCK SH CK1 CCD signal output 2 12 2 16 N 16 3 4 9 LCMP BTCMP="H" 16 S/H 34 9 GCAO signal output BLCMP N 8 8 BCMO signal output A/D clock A/D output N N 40 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CIS1 MODE) Register Address Bit Mode Signal Setting 00H D6 SENS D6 LCMPS D5 BLS D4 BLCMPS 02H D3 CCD D2 CIS3 D1 CIS2 D0 CIS1 CIS1 0 0 0 0 0 0 0 1 SH CK1 CIS signal output LCMP="H" BTCMP="H" S/H GCAO signal output A/D clock A/D output Unit : 1/SYSCK SH CK1 16 10 4 2 16 N CIS signal output LCMP="H" BTCMP="H" 16 7 S/H 4 1 GCAO signal output N A/D clock A/D output N 41 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CIS2 MODE) Register Address Bit Mode Signal Setting 00H D6 SENS D6 LCMPS D5 BLS D4 BLCMPS 02H D3 CCD D2 CIS3 D1 CIS2 D0 CIS1 CIS2 0 0 0 0 0 0 1 0 SH CK1 CIS signal output LCMP="H" BTCMP="H" S/H GCAO signal output A/D clock A/D output SH CK1 Unit : 1/SYSCK 16 10 4 2 16 N CIS signal output LCMP="H" BTCMP="H" 16 7 S/H 4 1 GCAO signal output A/D clock N A/D output N 42 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CIS3 MODE) Register Address Bit Mode Signal Setting 00H D6 SENS D6 LCMPS D5 BLS D4 BLCMPS 02H D3 CCD D2 CIS3 D1 CIS2 D0 CIS1 CIS3 1 1 0 1 0 1 0 0 Non-signaling part Shielding pixel part Effective pixel part SH CK1 CIS signal output LCMP BTCMP="H" S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Unit : 1/SYSCK Non-signaling part Shielding pixel part Effective pixel part SH CK1 CIS signal output LCMP BTCMP="H" 16 16 16 N 10 4 2 4 7 1 S/H 4 1 GCAO signal output 8 8 N BLCMP BCMO signal output A/D clock N N A/D output 43 M a x .500mVpp. 44 0.1F LEVAJ=VBL BCMV=VBL GCAO LEVAJ BCMV C1C2 BCMI BCMO (bold line) : signal line (dashed line) : clock line VCC H AVCC DVCC VCC 4 AVDD S/H BTCMPBLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sample and hold circuit - + + - - + MCIS <3:1>, MCCD - + MCIS1 0.1F GCA + - - + - + + - AIN AIN Level shift circuit(2.2V) MCIS2 MCIS3 8 AGCSEL <7:0> Gain control circuit Black level clamping circuit Sensor output LCMP - + Black 2.2V - + MCCD - + Bit clamping circuit LCMP MCIS <3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN <7:0> White Input clamping circuit Signaling element Blanking element Reference voltage generating circuit for the A/D converter + - + - Digital circuit Internal reference voltage source for the analog circuits VriAVCC DVCC Vref- Vri+ Vref+ AGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET 1.8V 3.8V AGND VriVri+ VBL VWL ADIN DGND OF DIN <6:0> GND FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI DIGITAL ASSP M66335FP AGND DGND GND Fig. 18 External pin connections of the analog part (for the CCD mode/bit clamping) 0.1F LEVAJ=VBL BCMV=VBL AVCC DVCC VCC (bold line) : signal line (dashed line) : clock line GCAO LEVAJ BCMV C1C2 BCMI BCMO 4 VCC H L AVDD S/H BTCMPBLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sample and hold circuit - + + - - + MCIS <3:1> ,MCCD - + MCIS1 0.1F GCA + - - + - + + - AIN AIN Level shift circuit(2.2V) MCIS2 MCIS3 8 Gain control circuit Black level clamping circuit AGCSEL <7:0> LCMP - + Black 2.2V - + MCCD - + Bit clamping circuit LCMP MCIS <3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN <7:0> M a x .500mVpp. White Input clamping circuit Blanking element Signaling element Reference voltage generating circuit for the A/D converter + - + - Digital circuit Internal reference voltage source for the analog circuits VriAVCC Vref- Vri+ DVCC Vref+ AGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET 1.8V 3.8V AGND VriVri+ VBL VWL ADIN DGND OF DIN <6:0> GND AGND DGND GND FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI DIGITAL ASSP M66335FP 45 Fig. 19 External pin connections of the analog part (for the CCD mode/line clamping) Black White 46 Max.5pF GCAO LEVAJ BCMV BCMI BCMO (bold line) : signal line (dashed line) : clock line BCMV=VBL C1C2 VCC H L L AVCC DVCC VCC 4 H AVDD S/H BTCMPBLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sample and hold circuit - + + - - + MCIS<3:1>,MCCD - + MCIS1 Level shift circuit(2.2V) Sensor output AIN GCA - + + - + - - + MCIS2 MCIS3 8 Gain control circuit Black level clamping circuit AGCSEL<7:0> Sensor output Max.3.5V LCMP - + MCCD - + Bit clamping circuit 2.2V - + Input clamping circuit LCMP MCIS<3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN<7:0> 200mV Reference voltage generating circuit for the A/D converter + - + - Digital circuit Internal reference voltage source for the analog circuits VriAVCC DVCC OF DIN<6:0> Vref- Vri+ Vref+ AGND Set R1 and R2 so that the following equation will hold. VLEVAJ = VVBL - A ! B + 0.2 [V] (1.8V) where, A : minimum limit for dark voltage of the sensor 1.8V 3.8V Gr : gain of the gain control circuit VREFH OF VREFL B<7:1> ADIN A/D converter ADCK RESET AGND VriV LEVAJ Vri+ VBL VWL R1 R2 ADIN DGND GND FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI DIGITAL ASSP M66335FP AGND DGND GND Fig. 20 External pin connections of the analog part (for the CIS1 mode) Max.5pF (In the case of the pixel clock of 1 MHz) C1C2 (dashed line) : clock line GCAO LEVAJ BCMV BCMI BCMO (bold line) : signal line BCMV=VBL AVCC DVCC VCC 4 VCC H L L H AVDD S/H BTCMPBLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sample and hold circuit - + + - - + MCIS<3:1>, MCCD - + MCIS1 AIN GCA - + + - - + + - AIN Level shift circuit(2.2V) MCIS2 MCIS3 8 Gain control circuit Black level clamping circuit AGCSEL<7:0> Sensor output M a x .2V LCMP - + - + MCCD Black White Input clamping circuit 2.2V - + Bit clamping circuit LCMP MCIS<3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN<7:0> 200mV Reference voltage generating circuit for the A/D converter + - + - Digital circuit Internal reference voltage source for the analog circuits VriAVCC DVCC OF DIN<6:0> Vref- Vri+ Vref+ AGND Set R1 and R2 so that the following equation will hold. VLEVAJ = VVBL - A ! B + 0.2 [V] (1.8V) where, A : minimum limit for dark voltage of the sensor 1.8V 3.8V Gr : gain of the gain control circuit VREFH OF VREFL B<7:1> ADIN A/D converter ADCK RESET AGND VriV LEVAJ Vri+ VBL VWL R1 R2 ADIN DGND GND AGND DGND GND FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI DIGITAL ASSP M66335FP 47 Fig. 21 External pin connections of the analog part (for the CIS2 mode) M a x .2Vpp. 48 0.1F LEVAJ=VBL BCMV=VBL C1C2 (dashed line) : clock line GCAO LEVAJ BCMV BCMI BCMO (bold line) : signal line VCC H L AVCC DVCC VCC 4 AVDD S/H BTCMPBLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sample and hold circuit - + + - - + MCIS <3:1>,MCCD - + MCIS1 0.1F GCA + - - + - + + - AIN AIN Level shift circuit(2.2V) MCIS2 MCIS3 8 AGCSEL <7:0> Gain control circuit Black level clamping circuit Sensor output LCMP - + White 2.2V - + MCCD - + Bit clamping circuit LCMP MCIS <3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN <7:0> Black Input clamping circuit Shielding pixel part Signalding part Reference voltage generating circuit for the A/D converter + - + - Digital circuit Internal reference voltage source for the analog circuits VriAVCC DVCC OF DIN Vref- Vri+ Vref+ AGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET 1.8V 3.8V AGND VriVri+ VBL VWL ADIN DGND <6:0> GND FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI DIGITAL ASSP M66335FP AGND DGND GND Fig. 22 External pin connections of the analog part (for the CIS3 mode) MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR FLOWCHART: READING OPERATIONS (FOR THE CCD SENSOR) Start Power on Software reset S/H: SH pulse width Sensor control Cycle counter Start pulse Image processing parameters Writing the dither pattern N Completed? Y writing correction table N Next original sheet The light source is turned on. (white reference) Becomes stable. 1 line cycle x20 (or 16 or more) wait Completed? Y AGC starts. Register 00 AGC: 16 times AGC ends. Uniformity correction starts. 1 line cycle x10 (or 8 or more) wait Uniformity correction ends. Register 00 Register 00 White correction : 8 times Register 00 Peak value detection Register 0F Register 00 Register 01 Reading an original sheet starts. Register 02 Register 03 and 04 SRDY setting Register 05 Initial setting Register 08 to 0E Register 10 N INT generated? Y N Page end? Y Reading the original sheet ends. Y 1 line cycle x 2 wait The light source is turned off. N Next original sheet Y Next original sheet? Transfer to be continued? A Image processing function Register 06 and 07 Register 00 Reading a single page Specifying the scaling factor for vertical scanning Register 15 Register 16 Register 17 Register 00 N Y Power off? White correction N Power off End Specifying the vertical scanning resolution Register 06 Setting for the original sheet Specifying the horizontal scanning resolution N Completed? Y Specifying the vertical scanning resolution Original sheet width and output width Register 15 Register 06 Registers 01 and 11 to 14 A 49 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR READING OPERATIONS (FOR THE CIS SENSOR) Start Power on Software reset S/H: SH pulse width Sensor control Cycle counter Start pulse Image processing parameters Writing the dither pattern N Completed? Y writing correction table N Next original sheet The light source is turned on. (white reference) Becomes stable. 1 line cycle x 20 (or 16 or more) wait The light source is turned off. Black correction Becomes stable. Uniformity correction mode (black) Uniformity correction starts. 1 line cycle x10 (or 8 or more) wait The light source is turned on. (white reference) Becomes stable. Registers 00 and 01 Power off End Completed? Y Peak value detection AGC starts. Register 00 AGC: 16 times AGC ends. Register 00 Register 0F 1 line cycle x 2 wait The light source is turned off. Y Register 00 Register 01 Reading an original sheet starts. Register 02 Registers 03 and 04 SRDY setting Initial setting Register 05 Registers 08 to 0E Register 10 N Register 16 Specifying the scaling factor for vertical scanning Register 00 Reading a single page A Image processing function Register 06 and 07 Register 15 INT generated? Y Register 17 N Page end? Y Reading the original sheet ends. Y Transfer to be continued? Register 00 N Power off? N Y Next original sheet Next original sheet? N Register 00 Black correction: 8 times Uniformity correction ends. Uniformity correction mode (white) Uniformity correction starts. Register 00 White correction Registers 00 and 01 Register 00 White correction: 8 times 1 line cycle x10 (or 8 or more) wait Uniformity correction ends. Register 00 Specifying the horizontal scanning resolution Writing the resolution change table N Completed? Register 06 Setting for the original sheet Register 15 Y Specifying the vertical scanning resolution Original sheet width and output width Register 06 Registers 01 and 11 to 14 A 50 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ABSOLUTE MAXIMUM RATINGS (Ta = -20 ~ 75C unless otherwise noted) Symbol VCC VI VO AVCC DVCC VWL VBL VAIN Tstg Supply voltage Input voltage Output voltage Analog supply voltage Supply voltage Reference voltage (white) Reference voltage (black) Analog input voltage Storage temperature Parameter Conditions Ratings -0.3 ~ +6.5 -0.3 ~ VCC+0.3 0 ~ VCC VCC -0.3 ~ VCC +0.3 VCC -0.3 ~ VCC +0.3 -0.3 ~ AVCC +0.3 -0.3 ~ AVCC +0.3 -0.3 ~ AVCC +0.3 -55 ~ +150 Unit V V V V V V V V C RECOMMENDED OPERATIONAL CONDITIONS Symbol VCC GND VI AVCC AGND DVCC DGND VAIN Topr Parameter Supply voltage (for the digital system component) GND voltage Input voltage Analog supply voltage Analog GND voltage Supply voltage (for the digital system component) GND voltage Input range: VWL AVcc; VBL AGND Operating temperature 1.8 -20 4.75 0 4.75 5.0 0.0 5.0 0.0 2.0 2.2 +75 5.25 Limits Min. 4.75 Typ. 5.0 0.0 VCC 5.25 Max. 5.25 Unit V V V V V V V VP-P C Note: Connect the analog system component and the digital system component separately to power supply on the evaluation board for noise prevention. 51 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 75C, VCC = 5V5% unless otherwise noted) Symbol VIH VIL VT+ VT- VH VOH VOL VOH VOL IIH IIL IOZH IOZL IAIN RL Ed ICCS "H" input voltage "L" input voltage Positive direction input threshold Negative direction input threshold Hysteresis value "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" input current "L" input current "H" input current in the off state "L" input current in the off state Analog input current Reference resistance Differential non-linear error Static current dissipation (during standby) VCC = 5.25V VI = VCC, GND 120 1.0 21 35 IOH = -12mA IOL = 12mA IOH = -4mA IOL = 4mA VCC = 5.25V VI = 5.25V VCC = 5.25V VI = 0V VCC = 5.25V VO = 5.25V VCC = 5.25V VO = 0V VCC-0.8 0.55 1.0 -1.0 5.0 -5.0 1.0 VCC-0.8 0.55 0.6 0.2 Parameter Test conditions Ratings Min. 2.0 0.8 2.4 Typ. Max. Unit V V V V V V V V V mA mA mA mA mA LSB mA 52 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR TIMING CONDITIONS (Ta = -20 ~ 75C, VCC = 5V5% unless otherwise noted) Symbol tc (SYS) tw+ (SYS) tw- (SYS) tr (SYS) tf (SYS) tw (RD) tsu (CS-RD) tsu (A-RD) tsu (DAK-RD) th (RD-CS) th (RD-A) th (RD-DAK) tw (WR) tsu (CS-WR) tsu (A-WR) tsu (D-WR) th (WR-CS) th (WR-A) th (WR-D) th (STIM-SRDY) System clock cycle System clock "H" pulse width System clock "L" pulse width System clock rise time System clock fall time Read pulse width Set-up time before read Set-up time before read Set-up time before read Hold time after read Hold time after read Hold time after read Write pulse width Set-up time before write Set-up time before write Set-up time before write Hold time after write Hold time after write Hold time after write Hold time after STIM CS A0 ~ A4 D0 ~ D7 CS A0 ~ A4 D0 ~ D7 SRDY CS A0 ~ A4 DAK CS A0 ~ A4 DAK 100 20 20 20 10 10 10 100 20 20 50 20 10 0 0 Parameter Test conditions Ratings Min. 50 25 25 20 20 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 53 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR SWITCHING CHARACTERISTICS (Ta = -20 ~ 75C, VCC = 5V5% unless otherwise noted) Symbol tPZL (RD-D) tPZH (RD-D) tPLZ (RD-D) tPHZ (RD-D) tPHL (RD-DRO) __ __ __ __ __ Parameter Test conditions Ratings Min. Typ. Max. 75 Unit ns ns ns ns ns Enable time for data output after read CL = 150pF Disable time for data output after read Propagation time of DRO output after read CL = 50pF 10 50 50 TEST CIRCUIT Parameter SW1 Open Closed Closed Closed Open SW2 Open Open Closed Open Closed Input VCC Output VCC RL=1k SW1 SW2 tPLH, tPHL tPLZ tPHZ tPZL P.G Tested device CL GND tPZH 50 RL=1k (1) Characteristics (10% to 90%) of the pulse generator (PG): tr = 3ns; tf = 3ns (2) Capacitance CL (= 150pF) includes the stray capacitance of connections and input capacitance of the probe. SYSTEM CLOCK tc(SYS) tf(SYS) tW+(SYS) tW-(SYS) 3V 90% SYSCK 1.3V 1.3V 1.3V 10% 10% 0V 90% tr(SYS) 54 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR MPU INTERFACE 1) Timing for read operation (M66335 MPU) 3V CS 1.3V tSU(CS-RD) 1.3V th(RD-CS) 0V 3V A0~A4 1.3V tSU(A-RD) tW(RD) 1.3V th(RD-A) 0V 3V RD 1.3V tPZL(RD-D) D0~D7 50% tPZH(RD-D) D0~D7 90% 1.3V 0V tPLZ(RD-D) VOL 10% tPHZ(RD-D) VOH 50% 2) Timing for write operation (MPU M66335) 3V CS 1.3V tSU(CS-WR) 1.3V th(WR-CS) 0V 3V A0~A4 1.3V tSU(A-WR) tW(WR) 1.3V th(WR-A) 0V 3V WR 1.3V 1.3V 0V tSU(D-WR) tSU(WR-D) 3V D0~D7 1.3V Effective data 1.3V 0V 55 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR DMA TIMING Timing for read operation (M66335 system bus) VOH DRQ 50% 120/SYSCK tPHL(RD-DRQ) 3V DAK 1.3V tSU(DAK-RD) tW(RD) 1.3V 0V th(RD-DAK) 3V RD 1.3V tPZL(RD-D) D0~D7 50% tPZH(RD-D) D0~D7 90% 1.3V 0V tPLZ(RD-D) 50% VOL 10% tPHZ(RD-D) VOL VOH 50% Timing of CODEC th(STIM-SRDY) 3V SRDY 1.3V 0V VOH STIM 50% VOL VOH SCLK VOL VOH SVID VOL 56 MITSUBISHI DIGITAL ASSP M66335FP FACSIMILE IMAGE DATA PROCESSOR Cautions for Use (1) Access to Address 00h To gain access to address 00h, the value of built-in GCC (gain control counter) may be set to FFh. This requires to read GAIN value at address 18h before access to address 00h and write the GAIN value at address 18h after the access (see Flowchart A). Start Read GAIN value at address 18h Access address 00h Write GAIN value at address 18h End Flowchart A. Address 00h Access Flow (2) Reset The M66335FP adopts the two types of reset. These reset functions are provided in Table A. Table A. Reset functions Function Reset type Hardware reset (RESET) Software reset register 0 (RESET) Register initialization Internal F/F initialization GCC initialization 57 |
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